1. Field of the Invention
The present invention relates to processor data buses, and more particularly to a flexible width data protocol which solves the problem of large package and unreasonable power requirements for a present day microprocessor where a significant amount of pins and power are devoted to the data bus interface of the microprocessor.
2. Description of the Related Art
In a present day microprocessor, such as an x86-compatible microprocessor, transactions (i.e., read and write transactions) to/from memory are accomplished over a system bus. These transactions include a request phase and a data (i.e., response) phase. During the request phase, an address for a transaction along with the transaction type are provided over an address signal group. The address signal group typically includes an address bus, a set of corresponding address strobe signals, and a request bus. During the data phase, data corresponding to the transaction is transferred over a data signal group. The data signal group typically includes a data bus, a set of corresponding data strobe signals, a response bus (indicating the type of response), and bus control signals. In one particular conventional configuration, the data signal group includes about 72 or so signals which must be provided on pins of a package for the microprocessor die. Many conventional configurations support “quad-pumped” transactions in which an entire cache line (e.g., eight quadwords for a 64-byte cache line) is transferred across the bus in just a few cycles (e.g., two clock cycles) of a bus or system clock. During the quad-pumped transactions for the conventional microprocessor, most of the signals of the data signal group are asserted multiple times during each clock cycle, consuming a considerable amount of power.
The present inventor has noted that the conventional data signal group configuration is problematic in certain application areas where package size and/or power are constrained. It is therefore desirable to provide a mechanism whereby the number of data signal group pins and commensurate power requirements are reduced, but where the data transfer functionality is retained. Furthermore, to accommodate varying application areas, it is desirable to provide a mechanism whereby a data transferring capability can be configured in either a full-width data bus mode as described above or in a new half-width data bus mode, as will be described herein.